Anais do IX SIBGRAPI'96 (1996), -



Dedicated Parallel Architectures for Image Processing

M. Akil

Groupe ESIEE - Computer Science Departement

akilm@esiee.fr


Abstract:
Implementating an image oriented computer architecture is often done with a view to the real-time execution of the application.

Depending on the processing, the involved data structures and the communication needs, an image processing application can be divided into three levels: low, medium and high.

Usually, for low-level, the steps are simple and repetitive, the number of these steps is constant and the data exchange, handled in a static way, is regular and locally done.

At medium-level, the steps are recursive, iterative, and their number is changeable. Data exchanges have an uneven rate, their type is global and depends upon the image content. It is the same thing for high-level operations.

So the 2D mesh systems are well adapted for low-level local processing. The communication network optimizes communication between neighbouring processors. Their main drawbacks are: first, their rather high diameter which downgrades global communications, and second, the processor array size is less than the image size which leads to a time costly sequential processing.

Pyramidal structures allow integrating and transmitting information in a logarithmic time scale. They optimize local processing (in a given structure slice level) and distant data exchange: concentrating and transmitting information thanks to the upwards and downwards movements. However some problem remain, typically about implementation and Multi-SIMD control mode handling.

Reconfigurable architectures based upon spatial rearragement, implement various communication types such as local, ascending and descending movements. They make global operations on local set of connected EPs (Elementary Processors). The result is transmitted in an asynchronous way to each EP in every set.

From the study of existing dedicated machines, one can see however, some specific characteristics: first, the heteregeneous mode (capable of making several execution models run together efficiently), and second, the reconfigurable models.

In this way, specific processors with reconfiguration capabilities work together with general processors, for medium and high-level operations.